1. Field of the Invention
The present invention relates to IC memory cards that comply with PC card standards and are used as external storage media for information processing equipment such as notebook personal computers, portable terminal units, and the like.
2. Description of the Related Art
FIG. 16 is a block diagram illustrating an example of prior IC memory cards. Referring to FIG. 16, an IC memory card 200 comprises an interface section 202 that complies with PC card standards and interfaces with a host system apparatus 201, a common memory section 203 that stores data from host system apparatus 201 and consists of SRAM or flash memory or the like, an attribute memory section 204 that stores attribute information about IC memory card 200, and a power-supply control circuit 205 that provides to each section of IC memory card 200 externally input source power and also generates and outputs a reset signal.
Interface section 202 is composed of an address bus buffer 207, an address decoder 208, a card mode controller 209, and a data bus buffer 210. The connection between IC memory card 200 and host system apparatus 201 is, for example, made by a plug-and-socket connector that is formed of male and female connector members, so that interface section 202 usually contains the female connector member. However, the connectors are omitted from FIG. 16.
Address bus buffer 207 and address decoder 208 are connected to the host system apparatus 201 through an address bus 211; card mode controller 209 is connected to the host system apparatus 201 through a control bus 212; and data bus buffer 210 is connected to the host system apparatus 201 through a data bus 213. Power-supply control circuit 205 is connected to the host system apparatus 201. Power-supply control circuit 205 is connected to address bus buffer 207, card mode controller 209, and data bus buffer 210 through a reset signal line, onto which a reset signal /RES is output. Power-supply control circuit 205 is also connected to each section through a power line, onto which a source voltage Vcc is output. However, these connections are omitted from FIG. 16.
Further, address bus buffer 207 is connected to common memory section 203 through an internal address bus 214. Card mode controller 209 is connected to common memory section 203, attribute memory section 204, and data bus buffer 210 through a plurality of signal lines 215. Data bus buffer 210 is connected to common memory section 203 and attribute memory section 204 through an internal data bus 216. Address decoder 208 is connected to card mode controller 209.
In this construction, power-supply control circuit 205 provides to each section the source power input through interface section 202 from host system apparatus 201. Power-supply control circuit 205 genrates a reset signal /RES to output to address bus buffer 207, card mode controller 209, and data bus buffer 210, when the source power input from host system apparatus 201 rises to HIGH level and falls to LOW level.
Address bus buffer 207 receives address data from host system apparatus 201 through address bus 211 and outputs the input address data into common memory section 203 and attribute memory section 204 through internal address bus 214. Further, address decoder 208 receives the address data from host system apparatus 201 and decodes the address data to output a control signal into card mode controller 209 and outputs a chip select signal into common memory section 203 and attribute memory section 204.
In addition to the control signal from address decoder 208, card mode controller 209 is also provided with a card-mode control signal comprising an output enable signal, a write enable signal, a card enable signal, and a memory-space select signal and the like through control bus 212. Here, the memory-space select signal selects one of the memory spaces of common memory section 203 and attribute memory section 204. Card mode controller 209 then generates from these signals a memory control signal, which consists of an output enable signal, a write enable signal, a chip select signal, and the like, for controlling common memory section 203 and attribute memory 204, and also generates an I/O control signal. Card mode controller 209 then outputs the memory control signal into common memory section 203 and attribute memory section 204 through signal lines 215 and outputs the I/O control signal into data bus buffer 210.
Data bus buffer 210 performs I/O control, on data bus 213 and internal data bus 216, of data between host system apparatus 201 and common memory section 203 and of data between host system apparatus 201 and attribute memory section 204, based on the I/O control signal input from card mode controller 209. Further, common memory section 203 and attribute memory 204 perform the writing and reading of data through internal data bus 216, based on the address data input through internal address bus 214 and the memory control signal input through signal lines 215.
The IC memory card described above can be used with host system apparatus produced by a plurality of manufacturers, as far as they are compatible with the architecture of the IC memory card. Also, those who have access to the memory content of the IC memory card are not limited to the users of a particular host system apparatus. Therefore, as long as the host system apparatus runs on the same operating system, any one who has a knowledge of the operating system can freely read data out from common memory section 203 and write data into common memory section 203, when the IC memory card is used as an external storage medium. That means there has been a problem of being unable to maintain security of the data stored in common memory section 203.